/*!
    \file    readme.txt
    \brief   description of the TIMERs cascade synchro demo

    \version 2026-02-05, V1.3.0, firmware for gd32c2x1
*/

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*/

  This example is based on the GD32C231C-EVAL-V1.0 board, it shows 
how to synchronize TIMER peripherals in cascade mode.

  /* timers synchronisation in cascade mode ----------------------------
  1/TIMER2 is configured as master timer:
  - PWM mode is used
  - The TIMER1 update event is used as trigger output  

  2/TIMER0 is slave for TIMER2,
  - PWM mode is used
  - The ITI0(TIMER2) is used as input trigger 
  - external clock mode is used,the counter counts on the rising edges of
  the selected trigger.
  - the TIMER1 update event is used as trigger output. 

  -------------------------------------------------------------------- */
  The TIMxCLK frequency is set to CK_AHB 48MHz the prescaler is 48, so the TIMER2
counter clock is 1MHz.

  The master timer TIMER2 is running at TIMER2 frequency :
  TIMER1 frequency = (TIMER2 counter clock)/ (TIMER2 period + 1) = 1000 Hz 
and the duty cycle = TIMER2_CH0CC/(TIMER2_CAR + 1) = 50%

  The TIMER1 is running:
  - At (TIMER1 frequency)/ (TIMER1 period + 1) = 500 Hz and a duty cycle
    equal to TIMER1_CH0CC/(TIMER1_CAR + 1) = 50%
