/*!
    \file    readme.txt
    \brief   description of RAMECCMU example

    \version 2026-02-04, V1.3.0, firmware for GD32H75E
*/

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  This example is based on the GD32H75EY-EVAL-V1.0 board, it shows how to use RAMECCMU 
to deal with single ECC error in AXI_SRAM. 
  
  The main steps are shown as below: 
  (1) AXI_SRAM is memset to all zeros.
  (2) AXI_SRAM's corresponding RAMECCMU peripheral RAMECCMU0 is deinitialized to reset status.
  (3) Enable ECC error latching and ECC single error interrupt for RAMECCMU0 Monitor0,
      enable global ECC single error interrupt.
  (4) Write AXI_SRAM in double word unit with a certain data pattern '0xAAAAAAAAAAAAAAAA'.
  (5) Read AXI_SRAM in double word unit and check ECC status.
  (6) If a single ECC error has been monitored, it will trigger an ECC single error interrupt
      and 'single_ecc_error_corret_flag' will be set to '1' in 'RAMECCMU_IRQHandler' interrupt service
      routine, user can get ECC failing address and ECC failing data by reading RAMECCMU0 Monitor0
      register as well.
  (7) If none single ECC error monitored, the value of 'single_ecc_error_occur_times' will be zero.
