/*!
    \file    readme.txt
    \brief   description of the TIMERs cascade synchro demo for GD32G5x3

    \version 2025-07-15, V1.0.0, firmware for GD32G5x3
*/

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  This demo is based on the GD32G553Q-EVAL-V1.0 board, it shows how to synchronize TIMER
peripherals in cascade mode.

  In this example three timers are used:
  1/TIMER1 is configured as master timer:
  - PWM mode 0 is used
  - The TIMER1 update event is used as trigger output 0

  2/TIMER7 is slave for TIMER1 and master for TIMER0:
  - PWM mode 0 is used
  - The ITI1 (TIMER1) is used as input trigger
  - External clock mode is used, the counter counts on the rising edges of the selected
    trigger.
  - The TIMER7 update event is used as trigger output 0.

  3/TIMER0 is slave for TIMER7:
  - PWM mode 0 is used
  - The ITI14 (TIMER7) is used as input trigger
  - External clock mode is used, the counter counts on the rising edges of the selected
  trigger.

  The frequency of TIMER1 is fixed to 216MHz, TIMER1 counter clock is: 216MHz/1080= 200 KHz.

  The master timer TIMER1 is running at:
  - TIMER1 frequency = (TIMER1 counter frequency)/ (TIMER1 period + 1) = 50Hz
  - duty cycle = TIMER1_CH0CV/(TIMER1_CAR + 1) = 50% (PA5: TIMER1 CH0).

  The TIMER7 is running at:
  - TIMER7 frequency = (TIMER1 frequency) / (TIMER7 period + 1) = 25Hz
  - duty cycle = TIMER7_CH0CV / (TIMER7_CAR + 1) = 50% (PC6: TIMER7 CH0).

  The TIMER0 is running at:
  - TIMER0 frequency = (TIMER7 frequency) / (TIMER0 period + 1) = 12.5Hz
  - duty cycle = TIMER0_CH0CV / (TIMER0_CAR + 1) = 50% (PA8: TIMER0 CH0).
