/*!
    \file    readme.txt
    \brief   description of the TIMER0 dma burst demo for GD32G5x3

    \version 2025-07-15, V1.0.0, firmware for GD32G5x3
*/

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*/

  This demo is based on the GD32G553Q-EVAL-V1.0 board, it shows how to use DMA with
TIMER0 update request to transfer data from memory to TIMER0 capture compare register
0~3.

  TIMER0 frequency is fixed to 216MHz, TIMER0 prescaler is equal to 216, so TIMER0
counter frequency is 1MHz.

  The objective is to configure TIMER0 channel 0~3 (PC0 / PC1 / PC2 / PC3) to generate
PWM signals. Capture compare register 0~3 are to be updated twice per circle.

  On the first update DMA request, data1 is transferred to CH0CV, data2 is transferred
to CH1CV, data3 is transferred to CH2CV, data4 is transferred to CH3CV and duty cycles
are (10 %, 20 %, 30 %, 40 %).

  On the second update DMA request, data5 is transferred to CH0CV, data6 is transferred
to CH1CV, data7 is transferred to CH2CV, data8 is transferred to CH3CV and duty cycles
are (50 %, 60 %, 70 %, 80 %).
