/*!
    \file    readme.txt
    \brief   debug TIMER2 when the MCU is in debug mode

    \version 2025-08-01, V1.0.0, firmware for gd32c2x1
*/

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*/

  This demo is based on the GD32C231C-EVAL-V1.0 board, it shows that,
when the TIMER2_HOLD bit in DBG control register(DBG_CTL) is set and the core halted, the TIMER2
counter stop counting and the PWM outputs of all channels are stopped as well. It's benefit
for debuging.

  The TIMER2 counter clock used is 1MHz. If the code is running normally, LED1 will be toggled in 1s cycles.

The Three Duty cycles are computed as the following description:
The channel 1 duty cycle is set to 25%.
The channel 2 duty cycle is set to 50%.
The channel 3 duty cycle is set to 75%.

  Connect the TIMER2 pins to an oscilloscope and monitor the different waveforms:
- TIMER2_CH1  pin (PB3)
- TIMER2_CH2  pin (PB6)
- TIMER2_CH3  pin (PB7)

  For Keil or IAR, in debug mode, when the core is stopped, update the register window for TIMER2,
you will see that the count value will not change. And at the same time, the PWM outputs of
all the channels of TIMER2 will be stopped.
