/*!
    \file    readme.txt
    \brief   description of the TIMER0 output asymmetric PWM and adc trigger for GD32M53x

    \version 2026-03-04, V1.0.0, firmware for GD32M53x
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice,
       this list of conditions and the following disclaimer in the documentation
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors
       may be used to endorse or promote products derived from this software without
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

  This demo is based on the GD32M531R-EVAL-V1.2 board, it shows how to configure TIMER0_CH0
 / CH1 in asymmetric PWM mode and TIMER0 adc trigger function.

  TIMER0 configuration:
  - CH0, CH1 output asymmetric PWM waveform.

  TIMER0 frequency = CK_TIMER/180 = 1MHz. The PWM frequency is 1MHz / (100 * 2) = 5KHz.
  - CH0 configuration in composite PWM mode, the high level duty cycle 30% (40 + 20) / 200).
  - CH1 configuration in composite PWM mode, the high level duty cycle 70% ((100 - 40 + 100 - 20) / 200).
  TIMER0_TRGA configuration:
  - Compare time��count up only
  - Repetiton value: 1
  - ADCCR1 register upadate event: TIMER_UPDATE_NEXT_OVERFLOW
  - ADC trigger signal monitoring function: use ADCSM1 pin and frequency is 1.25kHz (5kHz/2/2).
